Continuous time voltage regulators are quite popular today. Starting from a DC/DC converter, adopted for its superior efficiency performance, they provide a ripple-free power supply for a load circuit. This means that parameters like accuracy and PSRR are key features for this block as well as low power consumption. A continuous time regulator can be implemented accordingly to different requirements: either source or sink capability (usually not both), regulated voltage referenced to either GND or supply, possible low voltage drop between the regulated voltage and the supply or ground.
Among the possible implementations, with some dynamic range limitation, the so called capless approach is popular. It is based on a level shift and adopts a local feedback to reduce the output impedance and improve the load regulation performance. A low impedance node that drives the load is the major feature of this kind of solution. In this way, the output pole can be thought of as non-dominant making a load capacitor unnecessary. This gives a remarkable advantage in case the required regulated voltage is adopted for internal chip references, saving one pin where an external stabilizing capacitor is located. The capacitance of the capacitor is usually in the order of about hundreds nF that is too large to be integrated.
It is a desire to provide a level shift regulator circuit that has only a small area consumption and provides a high stability.